Complexities in DSP Software Compilation: Performance, Code Size Power, Retargetability

نویسندگان

  • Catherine H. Gebotys
  • Robert J. Gebotys
چکیده

This paper presents a new methodology for software compilation for embedded DSP systems. Although it is well known that conventional compilation techniques do not produce high quality DSP code, few researchers have addressed this area. Performance, estimated power dissipation, and code size are important design constraints in embedded DSP design. New techniques for code generation targeting DSP processors are introduced and employed to show improvements and applicability to different fixed point and floating point DSP popular architectures. Code is generated in fast cpu times and is optimized for minimum code size, energy dissipation, or maximum performance. Code generated for realistic DSP applications provide performance and code size improvements of up to 118% and measured power improvements of up to 49% for popular DSP processors compared to previous research and a commercial compiler. This research is important for industry since DSP software can be efficiently generated with constraints on code size, performance,

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

The Influence of DSP Processor Architectures on Code Compilation Difficulties

Today's DSP designers until recently were faced with the task of coding increasingly complex applications using inefficient compilers or tedious handgenerated assembly code. To make matters worse the products demanded low cost, extremely high performance and low power especially in the area of wireless communications and consumer markets. This paper examines the architectural features of severa...

متن کامل

A Study of Loop Unrolling for VLIW-based DSP Processors

With the growing popularity of DSPs and their associated applications, cost-effective software development has become a major issue. High-level language compilers are becoming more commonplace in the DSP world. While these compilers can generate correct code for DSP architectures, there remains considerable room for performance improvements. This paper addresses issues related to DSP compilatio...

متن کامل

ReXSim: A Retargetable Framework for Instruction-Set Architecture Simulation

Instruction-set simulators are an integral part of today’s processor and software design process. Due to increasing complexity of the architectures and time-to-market pressure, performance and retargetability are the most important features of an instruction-set simulator. Dynamic behavior of applications and processors requires the ISA simulators to be flexible. Flexible interpretive simulator...

متن کامل

Software Level Power Consumption Models and Power Saving Techniques for Embedded DSP Processors

Unlike DSP compilation for high performance, research for low power optimisation has received little attention, although power dissipation is a critical issue for mobile devices. This paper presents an overview of power consumption models and power saving techniques for embedded DSP processors applications and evaluates their application to the Texas Instruments TMS320VC5510 Digital Signal Proc...

متن کامل

Loop Transformations in the Ahead-of-Time Optimization of Java Bytecode

Loop optimizations such as loop unrolling, unfolding and invariant code motion have long been used in a wide variety of compilers to improve the running time of applications. In this paper we present a series of experimental results detailing the effect these techniques have on the running time of Java applications following ahead of time optimization. We also detail the optimization tools and ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1998